Four-transistor and five-transistor BJT-CMOS asymmetric SRAM cells
US8837204B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 15, 2010 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Nov 12, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell comprises asymmetric retention elements formed of bipolar junction transistors integrated with a CMOS transistor. The BJT transistors of the retention element may be vertically stacked. In one embodiment, the N region of two adjacent NPN BJT transistors may be connected to ground and may form a common emitter of the NPN BJT transistors while the P region of two adjacent PNP BJT transistors may be connected to high voltage and may form a common emitter of the PNP BJT transistors. For further compactness in one embodiment a base of one transistor doubles as a collector of another transistor. The retention element may have only a single bit line and a single write line, with no negative bit line. In some embodiments, a single inverter and only three transistors may form the retention element. Memory space may be cut approximately in half.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.