Patent · US Active

Local evaluation circuit for static random-access memory

US8837235B1 · kind B1 · utility

0Cited by

4References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Yuen H. Chan · Poughkeepsie, US
Michael Kugel · Eppelheim, DE
Silke Penth · Holzgerlingen, DE
Tobias Werner · Holzgerlingen, DE

Key dates

Filing date	Mar 6, 2013
Grant date	Sep 16, 2014
Priority date	—
Expiry date	Mar 6, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/4096
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A local evaluation circuit for a memory array includes first and second NAND gates and first, second, third, and fourth switches. The first switch is configured to couple a first node of the second NAND gate to a first power supply node in response to a first read signal. The second switch is configured to couple a first node of the first NAND gate to the first power supply node in response to a second read signal. The third switch is configured to couple a second node of the first NAND gate to a second power supply node in response to the first read signal. The fourth switch is configured to couple a second node of the second NAND gate to the second power supply node in response to the second read signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.