Dual mode clock/data recovery circuit
US8839020B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2012 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Jan 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0004
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.