Placement and area adjustment for hierarchical groups in printed circuit board design
US8839174B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 31, 2013 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Jan 31, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the invention are directed towards placing components within a layout design for a PCB. More specifically, various implementations of the invention provide methods and apparatuses that can dynamically adjust the shape or placement of component groups during an HGP process. With some implementations of the invention, an HGP process for planning the layout of a PCB is provided. Furthermore, component groups, which conflict, geographically, with either another component group or some other object within the layout design are allowed to be placed during the planning process. Subsequently, the placement locations for one or both of the conflicting component groups are adjusted to resolve the conflict. In some implementations, the geometric boundary, or footprint, of one or both of the component groups is adjusted to resolve the conflict.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.