Tool for evaluating clock tree timing and clocked component selection
US8839178B1 · kind B1 · utility
4Cited by
47References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Mar 14, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/396
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for generating timing constraints for an integrated circuit including a clock tree network are described. The techniques may be associated with a clock tree synthesis tool that receives a design of the integrated circuit and generates a clock tree network including a plurality of clocked components of the integrated circuit. The constraints may be generated as a function of the duration of propagation of a data signal from a transmitting clocked component coupled to a receiving clocked component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.