Method and apparatus for derived layers visualization and debugging
US8839183B2 · kind B2 · utility
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10References
21Claims
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Key dates
| Filing date | Jan 31, 2013 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Jan 31, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method, system and computer program product for visualizing derived layer shapes of an integrated circuit design are disclosed. The computer-implemented method, system and computer program product include visualizing the derived layer shapes on a layout canvas; providing a step by step process for visualizing each derived layer shape as each derived layer shape is generated; and providing a hierarchy of intermediate derived layers based upon the step by step process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.