Operation of a dual instruction pipe virus co-processor
US8839439B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2013 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Feb 7, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/031
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuits and methods are provided for detecting, identifying and/or removing undesired content. According to one embodiment, a method for virus processing content objects is provided. A content object is stored within a system memory by a general purpose processor using a virtual address. Most recently used entries of a page directory and a page table of the system memory are cached within a translation lookaside buffer (TLB) of a virus co-processor. Instructions are read from a virus signature memory of the co-processor. Those of a first type are assigned to a first of multiple instruction pipes of the co-processor. The first instruction pipe executes an instruction including accessing a portion of the content object by performing direct virtual memory addressing of the system memory using a physical address derived based on the virtual address and the TLB and comparing it to a string associated with the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.