Patent · US Active

Methods of forming silicide regions and resulting MOS devices

US8841192B2 · kind B2 · utility

1Cited by
25References
35Claims
0Family size

Assignee

Inventors

Key dates

Filing dateApr 11, 2012
Grant dateSep 23, 2014
Priority date
Expiry dateApr 11, 2032

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/038

Abstract

A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.