Static random access memory device including negative voltage level shifter
US8842464B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2011 |
| Grant date | Sep 23, 2014 |
| Priority date | — |
| Expiry date | Jun 27, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Integrated circuit memory devices include an array of static random access memory (SRAM) cells arranged as a plurality of columns of SRAM cells electrically coupled to corresponding plurality of pairs of bit lines and a plurality of rows of SRAM cells electrically coupled to a corresponding plurality of word lines. A word line driver and a column decoder are provided. The word line driver, which is electrically coupled to the plurality of word lines, is configured to drive a selected word line with a positive voltage and a plurality of unselected word lines with a negative voltage during an operation to write data into a selected one of the SRAM cells. The column decoder includes a plurality of pairs of selection switches therein, which are electrically coupled to corresponding ones of the plurality of pairs of bit lines. The column decoder is configured to drive control terminals of a first of the plurality of pairs of selection switches coupled to the selected one of the SRAM cells with positive voltages concurrently with driving control terminals of a second of the plurality of pairs of selection switches coupled to an unselected one of the SRAM cells with negative voltages duri…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.