Data phase locked loop circuit and method for generating frequency of reference signal thereof
US8842508B2 · kind B2 · utility
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1References
8Claims
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Key dates
| Filing date | Jun 6, 2007 |
| Grant date | Sep 23, 2014 |
| Priority date | — |
| Expiry date | Nov 27, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2220/2537
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A data phase locked loop circuit includes a phase locked loop circuit, a judging circuit, a detecting circuit and a control circuit. The phase locked loop circuit outputs a reference signal according to a data signal, which is generated by an optical drive reading an optical disk. When the judging circuit judges that a jitter signal is smaller than a threshold value, the control circuit stores a frequency of the reference signal. When the detecting circuit detects a defect zone of the optical disk read by the optical drive, the phase locked loop circuit fixes the frequency of the reference signal to a latest stored one.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.