Apparatus and method for reducing interference signals in an integrated circuit using multiphase clocks

US8842766B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Indu Prathapan · Bengaluru, IN
• Anjana Ghosh · Bengaluru, IN
• Diganta Baishya · Bengaluru, IN
• Sundarrajan Rangachari · Poonamallee, IN
• Sankar Prasad Debnath · Bengaluru, IN
• Ranjit Kumar Dash · Savanuru, IN
• Srinath Ramaswamy · Sachse, US

Key dates

• Filing date: Mar 31, 2010
• Grant date: Sep 23, 2014
• Expiry date: Apr 30, 2032

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F1/10
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An apparatus and method for reducing interference signals using multiphase clocks. An integrated circuit includes a digital circuit and an analog circuit. The digital circuit includes a derived clock circuit configured to receive a root clock having a frequency D*f, D being a divide factor, to divide the root clock by D, and generate multiphase clocks having N phases. N circuits of the digital circuit are configured to receive a corresponding one of the N phases, with edges of the multiphase clocks being spread over the N phases. The multiphase clocks cause a frequency shift in interference signals generated by reduced periodic peak currents drawn by the N circuits from f to N*f and harmonics thereof. The analog circuit receives an in-band range of signals. A value of N is configured to shift the interference signals outside the in-band range of signals.