Communication circuit and method of adjusting sampling clock signal
US8842793B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2011 |
| Grant date | Sep 23, 2014 |
| Priority date | — |
| Expiry date | Aug 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A communication circuit includes a sampling clock generating circuit generating a sampling clock signal having a frequency that is “m” times greater than a bit rate of the communication data and containing “n” pulses in each bit period of the communication data; and a sampling circuit sampling the communication data based on the sampling clock signal to obtain “n” sets of received data in each bit period of the communication data. The sampling clock generating circuit delays the sampling clock signal when a first one or more of the “n” sets of received data are different from a value of the rest of the “n” sets of received data, and advances the sampling clock signal when a value of a last one or more of the “n” sets of received data is different from a value of the rest of the “n” sets of received data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.