Display processing technique of design parameter space
US8843351B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2011 |
| Grant date | Sep 23, 2014 |
| Priority date | — |
| Expiry date | Oct 13, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This method includes: generating a constraint equation from data of an approximate expression of a cost function representing a relationship between a plurality of design parameters and a cost, data of a route in a cost space and data of a search range in a design parameter space; obtaining a logical expression of a solution for the constraint equation from a quantifier elimination processing unit that carries out a processing according to a quantifier elimination method; substituting coordinates of each of a plurality of points within the search range in the design parameter space into the logical expression of the solution to determine, for each of the plurality of points, true or false of the logical expression of the solution; and displaying the design parameter space in which a display object including a first point for which true is determined is disposed at the first point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.