Memory management among levels of cache in a memory hierarchy
US8843706B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2013 |
| Grant date | Sep 23, 2014 |
| Priority date | — |
| Expiry date | Feb 27, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/128
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, apparatus, and product for memory management among levels of cache in a memory hierarchy in a computer with a processor operatively coupled through two or more levels of cache to a main random access memory, caches closer to the processor in the hierarchy characterized as higher in the hierarchy, including: identifying a line in a first cache that is preferably retained in the first cache, the first cache backed up by at least one cache lower in the memory hierarchy, the lower cache implementing an LRU-type cache line replacement policy; and updating LRU information for the lower cache to indicate that the line has been recently accessed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.