Mechanism for detecting a no-processor swap condition and modification of high speed bus calibration during boot
US8843732B2 · kind B2 · utility
1Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2009 |
| Grant date | Sep 23, 2014 |
| Priority date | — |
| Expiry date | Nov 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2153
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory channel training parameters are function of electrical characteristics of memory devices, processor(s) and memory channel(s). Training steps can be skipped if the BIOS can determine that the memory devices, motherboard and processor have not changed since the last boot. Memory devices contain a serial number for tracking purposes and most motherboards contain a serial number. Many processors do not provide a mechanism by which the BIOS can track the processor. Described herein are techniques that allow the BIOS to track a processor and detect a swap without violating privacy/security requirements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.