Memory error protection using addressable dynamic ram data locations
US8843805B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2012 |
| Grant date | Sep 23, 2014 |
| Priority date | — |
| Expiry date | Sep 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In general, techniques are described for efficiently and transparently partitioning a physical address space of a DRAM part lacking dedicated error protection circuitry to supply addressable error protection bytes for use in detecting and/or correcting bit errors elsewhere present in the physical address space. In one example, a network device includes a DRAM and a memory controller that receives a write command to write data to the DRAM. An address translation module of the memory controller logically partitions the DRAM to define a plurality of physically addressable sections that includes an error protection section for storing error protection bits and one or more data storage sections. The memory controller defines a contiguous logical address space representing the data storage sections. A DRAM controller of the network device communicates with the DRAM to store the data to one of the data storage sections in accordance with the contiguous logical address space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.