Implementing voltage feedback gate protection for CMOS output drivers
US8847636B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2012 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | Nov 12, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit for implementing protection for complementary metal oxide semiconductor (CMOS) output drivers, and a design structure on which the subject circuit resides are provided. An output driver stage transistor stack includes a plurality of series connected PFETs series connected with a plurality of series connected NFETs connected between upper and lower voltage supply rails. A pair of offset DC voltage levels provides respective gate voltages of an intermediate PFET and an intermediate NFET in the output driver stage transistor stack. A pair of pre-driver circuits receiving voltage level translated logic signals drive respective gate inputs of the upper PFET and the lower NFET in the output driver stage transistor stack. A voltage feedback circuit provides respective gate voltages of the PFET and NFET connected together in the output driver stage transistor stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.