Mixed-mode receiver circuit including digital gain control
US8848110B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2010 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | Jun 25, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/52
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A receiver circuit includes an analog front-end and a digital processing unit. The analog front-end includes an input for receiving a radio frequency (RF) signal, a first control input for receiving a gain adjustment signal, a second control input for receiving a timing signal, and a signal output for providing a digital intermediate frequency (IF) signal. The analog front-end updates gains of a plurality of gain stages according to the gain adjustment signal and in synchronism with the timing signal. The digital processing unit is configured to produce at least one output signal derived from the digital IF signal. The digital processing unit includes a timing recovery circuit configured to generate the timing signal based on the digital IF signal to control timing of the updating gains of each of the plurality of adjustable gain stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.