Latch-based array with robust design-for-test (DFT) features
US8848429B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2013 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | Mar 7, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A latch-based memory includes a plurality of slave latches arranged in rows and columns. Each column of slave latches receives a latched data signal from a corresponding master latch. Each row includes a clock gating circuit and a corresponding reset circuit. If a row is active for a write operation, the active row's clock gating circuit passes a write clock to the active row's slave latches. Conversely, the clock gating circuit for an inactive row gates the write clock to the inactive row's slave latches by passing a held version of the write clock in a first clock state to the inactive row's slave latches. While a reset signal is asserted, each reset circuit gates the write clock by passing the held version of the write clock in the first clock state to the slave latches in the reset circuit's row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.