Low power memory controllers
US8848462B2 · kind B2 · utility
8Cited by
6References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2012 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | Jan 12, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller is provided. The memory controller is powered by first and second power source and includes an input/output pin, a driver circuit, a terminal resistor, and an input buffer. The driver circuit is coupled to the input/output pin and capable of providing to a writing signal to the input/output pin. The terminal resistor is coupled between the input/output pin and the first power source. The input buffer is coupled to the input/output pin and capable of receiving a reading signal from the input/output pin. No terminal resistor is coupled between the input/output pin and the second power source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.