Pulse width modulation receiver circuitry
US8848850B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 25, 2012 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | Mar 22, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K9/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Mechanisms and techniques to evaluate data for a high speed I/O receiver logic. In an embodiment, a receiver circuit shifts a bit into a shift circuit in response to a rising edge of a data signal, where a count is started in response to the bit being subsequently shifted out of the shift circuit. Based on a value of the count, the receiver circuit generates a control signal for preparing physical layer receiver logic to transition to a burst mode of operation. In another embodiment, a receiver circuit includes a frequency divider to operate based on a data signal and a clock signal, wherein, based on operation of the frequency counter, a control signal is generated to indicate a line reset for physical layer receiver logic. The receiver circuit provides a feedback signal, based on the control signal, which is to limit activation of the frequency divider.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.