Wireless receiver
US8849226B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 11, 2010 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | Jun 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/40
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A wireless receiver designed to conform to the standard IEEE 802.15.4. The receiver comprises an analog front-end and a digital decoder. The analog components of the front end include one or more amplifiers and an analog-to-digital converter (ADC). The digital decoder receives the output of the ADC and demodulates it in a demodulator which is driven at an a chip frequency by an internal or external clock. The demodulator comprises a sampler operable to sample the digital signal at a sampling frequency and a correlation unit operable to process a set of bits, referred to as a chip code, in the sampled digitized signal and output therefrom a set of correlation values. The set of correlation values is an indicator of likely mapping between the chip code that has been processed and a set of possible chip codes defined according to the standard. The demodulator further comprises a symbol selection unit and a frequency correction unit. The symbol selection unit has the function of deciding which symbol has been received based on an analysis of each set of correlation values. The frequency correction unit is operable to make adjustments to the chip frequency based on the correlation value…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.