System and method to reduce memory access latencies using selective replication across multiple memory ports
US8850101B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2013 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | Sep 11, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2532
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a system comprises a plurality of memory ports. The memory ports are distributed into a plurality of subsets, where each subset is identified by a subset index. The system further comprises a first address hashing unit configured to receive a request including at least one virtual memory address. Each virtual memory address is associated with a replication factor, and the virtual memory address refers to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address. The hardware based address refers to data in the memory ports within a subset indicated by the corresponding subset index.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.