System and method to provide non-coherent access to a coherent memory system
US8850125B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2011 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | May 29, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.