Compiler system, method and software for a resilient integrated circuit architecture
US8850411B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2007 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | Apr 29, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The exemplary embodiments provide a compiler for a reconfigurable integrated circuit having reconfigurable computational elements with a plurality of contexts. An exemplary compiler generates a compilation comprising a designation of a first type of reconfigurable computational element, the data input linkage or the data output linkage for a first action, and a portion of a first configuration for the first type of reconfigurable computational element comprising a first task identifier and the first action identifier. The reconfigurable integrated circuit utilizes the first task identifier and a run status designation in enabling and disabling corresponding contexts for execution by the reconfigurable computational elements. The first configuration, typically generated in a binding process, further comprises a first input data source address from the first data input linkage or a first output data destination address from the first data output linkage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.