Through silicon via packaging structures and fabrication method
US8853077B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2012 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Dec 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for fabricating a through silicon via packaging structure. The method includes providing a first type substrate, and forming a second type substrate deferent from the first type substrate on the first type substrate. The method also includes forming a semiconductor device on a first surface of the second type substrate, and forming an interlayer dielectric layer on the first surface of the second type substrate. Further, the method includes forming a metal interconnection structure in the interlayer dielectric layer, and forming a through silicon via structure perforating the second type substrate and electrically connecting with the metal interconnection structure. Further, the method also includes removing the first type substrate using a gas etching process or a wet etching process to expose a second surface of the second type substrate and a bottom surface of the through silicon via structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.