Semiconductor memory devices having lower and upper interconnections, selection components and memory components
US8853660B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2012 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Dec 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/882
Abstract
Semiconductor devices include lower interconnections, upper interconnections crossing over the lower interconnections, selection components disposed at crossing points of the lower interconnections and the upper interconnections, respectively, and memory components disposed between the selection components and the upper interconnections. Each of the selection components may include a semiconductor pattern having a first sidewall and a second sidewall. The first sidewall of the semiconductor pattern may have a first upper width and a first lower width that is greater than the first upper width. The second sidewall of the semiconductor pattern may have a second upper width and a second lower width that is substantially equal to the second upper width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.