ESD protection circuit
US8853784B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2013 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Jan 10, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
A device having a substrate defined with a device region which includes an ESD protection circuit is disclosed. The ESD protection circuit has first and second transistors. A transistor includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, and a second diffusion region in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. The device includes a first device well which encompasses the device region and second device wells which are disposed within the first device well. A well contact is coupled to the second device wells. The well contact surrounds the gates of the transistors and abuts the first diffusion regions of the transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.