Methods and apparatus for reducing coupling in a MOS device
US8853832B2 · kind B2 · utility
1Cited by
6References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 22, 2009 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Jun 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Mutual capacitances between regions of a MOS device become substantial factors that limit the speed and performance of the device as the device dimensions are reduced in size. A MOS transistor with a shielding structure formed above the gate is described. The shielding structure is connected to ground and is configured to reduce at least some of these mutual capacitances.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.