Level shifting circuit for high voltage applications
US8854106B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2013 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Jun 24, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018514
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifting circuit includes a current mirror that generates a first bias current and a second bias current (proportional to the first bias current with a first ratio). A first level shifter is coupled between a first input node (receiving a first input signal) and a first output node coupled to an input of the current mirror. The first level shifter applies a first voltage variation to the first input signal in response to the first bias current. A second level is coupled between a second input node (receiving a second input signal) and a second output node coupled to an output of the current mirror. The second level shifter applies a second voltage variation (associated with the first voltage variation) to the second input signal in response to the second bias current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.