Accelerating data packet parsing
US8854996B2 · kind B2 · utility
1Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2011 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Jan 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/10
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Mechanisms are provided for a network processor comprising a parser, the parser being operable to work in normal operation mode or in repeat operation mode, the parser in normal operation mode loading and executing at least one rule in a first and a second working cycle respectively, the parser in repeat operation mode being operable to repeatedly execute a repeat-instruction, the execution of each repeat corresponding to one working cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.