Updating non-shadow registers in video encoder
US8855194B2 · kind B2 · utility
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Key dates
| Filing date | May 9, 2011 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Jun 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/503
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A video processor controlled by a set of non-shadow registers is provided. A list of updates for one or more of the non-shadow registers may be prepared in a memory module. A frame buffer is updated with video data for a display coupled to the video processor. A blanking interval is detected after updating the frame buffer. A direct memory access engine is triggered to transfer the list of updates from the memory module to the non-shadow registers during the blanking interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.