Multi-processor architecture using multiple switch fabrics implementing point-to-point serial links and method of operating same
US8856421B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2012 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Dec 14, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-processor architecture for a network device that includes a plurality of barrel cards, each including: a plurality of processors, a PCIe switch coupled to each of the plurality of processors, and packet processing logic coupled to the PCIe switch. The PCIe switch on each barrel card provides high speed flexible data paths for the transmission of incoming/outgoing packets to/from the processors on the barrel card. An external PCIe switch is commonly coupled to the PCIe switches on the barrel cards, as well as to a management processor, thereby providing high speed connections between processors on separate barrel cards, and between the management processor and the processors on the barrel cards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.