Multi-core processor with internal voting-based built in self test (BIST)
US8856602B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2011 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | May 18, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2242
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit arrangement utilize scan logic disposed on a multi-core processor integrated circuit device or chip to perform internal voting-based built in self test (BIST) of the chip. Test patterns are generated internally on the chip and communicated to the scan chains within multiple processing cores on the chip. Test results output by the scan chains are compared with one another on the chip, and majority voting is used to identify outlier test results that are indicative of a faulty processing core. A bit position in a faulty test result may be used to identify a faulty latch in a scan chain and/or a faulty functional unit in the faulty processing core, and a faulty processing core and/or a faulty functional unit may be automatically disabled in response to the testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.