Semiconductor devices including vertical channel transistors and methods of fabricating the same
US8859363B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2011 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Feb 1, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of fabricating semiconductor devices may include forming first trenches in a substrate to define fin patterns and forming buried dielectric patterns filling lower regions of the first trenches. The first trenches extend in parallel. A gate dielectric layer is formed on upper inner sidewalls of the first trenches, and a gate conductive layer filling the first trenches is formed on the substrate including the gate dielectric layer. The gate conductive layer, the gate dielectric layer and the fin patterns are patterned to form second trenches crossing the first trenches and defining active pillars. Semiconductor devices may also be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.