Semiconductor device and method of manufacturing the same
US8859369B2 · kind B2 · utility
0Cited by
2References
5Claims
0Family size
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Key dates
| Filing date | Feb 7, 2013 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Feb 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/159
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor device having a vertical MOS transistor and a method of manufacturing the same. The vertical MOS transistor has a trench gate, a distance between a gate electrode and an N-type high concentration buried layer below the gate electrode is formed longer than that in the conventional structure, and a P-type trench bottom surface lower region (5) is formed therebetween. In this manner, when a high voltage is applied to a drain region and 0 V is applied to the gate electrode, the trench bottom surface lower region (5) is depleted, thereby increasing the breakdown voltage in the OFF state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.