Pixel matrix with compensation of ohmic drops on the power supplies
US8859979B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2008 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Oct 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/77
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A matrix microelectronic device includes elementary cells laid out according to a matrix. Each cell has a current source formed by a current source transistor. A source electrode of the transistor is connected to a source biasing conductor line of a plurality of source biasing conductor lines. A gate electrode of the transistor is connected to a gate biasing conductor line of a plurality of gate biasing conductor lines. A biasing device biases the gate biasing conductor lines and includes at least one first connection line that is connected to at least several of the gate biasing conductor lines. The biasing device includes a voltage generator or a current generator that causes a variation of potentials along the first connection line, thereby compensating a corresponding variation of potentials along the source biasing conductor lines. The device can include an addressing circuit for addressing horizontal lines or rows of the matrix.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.