Capacitor-less memory device
US8860109B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2009 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Mar 10, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6757
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a capacitorless memory device. The device includes a semiconductor substrate, an insulating layer disposed on the semiconductor substrate, a storage region disposed on a partial region of the insulating layer, a channel region disposed on the storage region to provide a valence band energy offset between the channel region and the storage region, a gate insulating layer and a gate electrode sequentially disposed on the channel region, and source and drain regions connected to the channel region and disposed at both sides of the gate electrode. A storage region having different valence band energy from a channel region is disposed under the channel region unit so that charges trapped in the storage region unit cannot be easily drained. Thus, a charge retention time may be increased to improve data storage capability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.