Fast dynamic register with transparent latch
US8860463B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 25, 2013 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Jul 25, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3872
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fast dynamic register including a data block, a precharge circuit, a transparent latch, and an output logic gate. The precharge circuit precharges first and second precharge nodes and then releases the first precharge node in response to a clock. The data block evaluates data by either pulling the first precharge node low in response to the clock or does not pull it low, in which case the second precharge node is discharged. The transparent latch passes a state of the second precharge node to a store node when transparent, and otherwise latches the store node. The output logic gate drives an output node to a state based on states of the second precharge node and the store node. The transparent latch may be implemented with relatively small devices to reduce size and power consumption to improve efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.