Fine grain data-based clock gating
US8860484B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Mar 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of a logic path are disclosed that may allow for a reduction in switching power. The logic path may include a storage circuit, a comparison circuit, and a clock gating circuit. The storage circuit may be configured to store received data responsive to a local clock signal. The comparison circuit may be operable to compare the received data to data previously stored in the storage circuit. The clock gating circuit may be configured to generate the local clock signal dependent on a global clock signal, and de-activate the local clock signal dependent upon the results of the comparison performed by the comparison circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.