Time-interleaved digital-to-time converter
US8860514B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2012 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Mar 24, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/131
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fractional-N divider supplies a divided clock signal. An adjusted divided clock signal is generated in a digital-to-time converter circuit having a delay linearly proportional to digital quantization errors of the fractional-N divider. The adjusted divided clock signal is generated based on first and second capacitors charging to a predetermined level. The charging of the first and second capacitors is interleaved in alternate periods of the divided clock. The charging of each capacitor with a current corresponding to respective digital quantization errors is interleaved with charging with a fixed current. A first edge of a first pulse of the adjusted divided clock signal is generated in response to the first capacitor charging to a predetermined voltage and a first edge of a next pulse of the adjusted divided clock signal is generated in response to the second capacitor charging to the predetermined voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.