Successive-approximation-register analog-to-digital converter for programmably amplifying amplitude of input signal and method thereof
US8860600B1 · kind B1 · utility
10Cited by
5References
21Claims
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Key dates
| Filing date | Aug 8, 2013 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Aug 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed are a successive-approximation-register (SAR) analog-to-digital converter (ADC) for programmably amplifying an amplitude of an input signal and a method thereof. During a sampling phase, a bottom plate of at least one capacitor in a capacitor array is connected electrically to an input signal, so that the capacitor array samples and amplifies the input signal, so as to lower a required sampling capacitor or reduce noise generation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.