Systems and methods for reducing leakage current in memory arrays
US8861283B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2012 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Nov 3, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are apparatus and devices for programming and operating a programmable memory array portion coupled with a leakage reduction circuit. At the leakage reduction circuit, a frame bias signal that indicates a majority state of the memory array portion can be received. During idle states of the programmable memory array portion, at least one shared bit line of the memory array portion can be selectively biased based on the received frame bias signal. In one aspect, a first one of two bit lines is biased to a first state, while the second one of the two bits lines is biased to a second state that is opposite the first state. In a further aspect, the first state is a same state as the majority state of the memory array portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.