Fault tolerant parallel receiver interface with receiver redundancy
US8861513B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2013 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Apr 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/113
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A communications parallel bus receiver interface having N+1 data lines and method of operation. The parallel bus interface employs receiver redundancy at the bus level such that there are N+1 receiver devices. One of the N+1 data signals comprising a spare data signal when a failure occurs in a corresponding channel transmitting one of N parallel data signals. An input switching network is configured to receive and couple N+1 parallel data signals along respective paths to corresponding parallel-configured bit receiver devices, and adapted to couple one received data signal to two or three adjacent bit receivers. A calibration device calibrates one of the two or three adjacent bit receivers, and a qualification device qualifies data decisions made during calibration processes performed by the calibration device. The method cycles through N+1 receivers for periodic recalibration of each receiver (one at a time) while N+1 inputs are processed continuously and uninterrupted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.