Hierarchical packing of syntax elements
US8861611B2 · kind B2 · utility
1Cited by
14References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2008 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Jan 19, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of operation within an integrated circuit device having a plurality of processing lanes. A first sub-stream of data, having a variable length, is generated in a first one of the processing lanes. A second sub-stream of data, also having a variable length, is generated in a second one of the processing lanes. The first and second sub-streams are then output to form a single bitstream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.