Receiving device and demodulation device
US8861648B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2010 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Aug 5, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0029
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
To adequately perform sampling, a receiving device that solves problems that involve an increase in circuit area and an increase in cost, is provided.A/D converter 2 samples a coherent signal that is an analog signal in synchronization with a sampling clock signal so as to convert the analog signal into a digital signal. DSP 3 demodulates the digital signal converted by A/D converter 2 and computes a phase of the sampling clock signal in which an error rate of the digital signal is the minimum based on the demodulated digital signal. Sampling clock extraction circuit 4 extracts a clock signal having a symbol rate of the coherent signal therefrom. Phase adjustment circuit 5 adjusts the phase of the clock signal extracted by sampling clock extraction circuit 4 to the phase computed by DSP 3 and generates a clock signal having the adjusted phase as the sampling clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.