Clock data recovery circuit with equalizer clock calibration
US8861667B1 · kind B1 · utility
17Cited by
275References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2002 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Jan 7, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03878
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A signal receiving circuit having an equalizer calibration function. The signal receiving circuit includes a sampling circuit, output driver and clock signal generator. The sampling circuit captures samples of a data signal in response to a sampling clock signal. The output driver outputs an equalizing signal to an input of the sampling circuit in response to a first clock signal. The clock signal generator adjusts a phase of the first clock signal to achieve phase alignment between transitions of the equalizing signal and transitions of the data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.