Dynamic sleep for multicore computing devices
US8862917B2 · kind B2 · utility
24Cited by
4References
76Claims
0Family size
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Key dates
| Filing date | Dec 6, 2011 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Mar 20, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The aspects enable a multi-core processor or system on chip to determine a low power configuration that provides the most system power savings by placing selected resources in a low power mode depending upon acceptable system latencies, dynamic operating conditions (e.g., temperature), expected idle time, and the unique electrical characteristics of the particular device. Each of the cores/processing units treated in a symmetric fashion, and each core may choose its operating state independent of the other cores, without performing complex handshaking or signaling operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.