Apparatus for at-speed testing, in inter-domain mode, of a multi-clock-domain digital integrated circuit according to BIST or SCAN techniques

US8862955B2 · kind B2 · utility

Assignee

• STMicroelectronics SA

Inventor

• Franco Cesari · Trezzano sul Naviglio, IT

Key dates

• Filing date: Dec 29, 2011
• Grant date: Oct 14, 2014
• Expiry date: Jul 12, 2032

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318594
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

An embodiment is directed to extended test coverage of complex multi-clock-domain integrated circuits without forgoing a structured and repeatable standard approach, thus avoiding custom solutions and freeing the designer to implement his RTL code, respecting only generally few mandatory rules identified by the DFT engineer. Such an embodiment is achieved by introducing in the test circuit an embodiment of an additional functional logic circuit block, named “inter-domain on chip clock controller” (icOCC), interfaced with every suitably adapted clock-gating circuit (OCC), of the different clock domains. The icOCC actuates synchronization among the different OCCs that source the test clock signals coming from an external ATE or ATPG tool and from internal at-speed test clock generators to the respective circuitries of the distinct clock domains. Scan structures like the OCCs, scan chain, etc., may be instantiated at gate pre-scan level, with low impact onto the functional RTL code written by the designer.