Method and system for error management in a memory device
US8862973B2 · kind B2 · utility
89Cited by
3References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2009 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Oct 26, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.